{"product_id":"huins-mfp-vp1802-s-versal-premium-vp1802-adaptive-soc-asic-rapid-prototyping-platform","title":"HUINS MFP-VP1802-S: Versal Premium VP1802 Adaptive SoC \u0026 ASIC Rapid Prototyping Platform","description":"\u003cul\u003e\n\u003cli\u003e\u003ca href=\"#description\"\u003eDescription\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#fpga-specification\"\u003eFPGA Specification\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#features\"\u003eFeatures\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#whats-included\"\u003eWhat's Included\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#resources-downloads\"\u003eResources \u0026amp; Downloads\u003c\/a\u003e\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch4 id=\"description\"\u003eDescription\u003c\/h4\u003e\n\u003cp\u003eHUINS MFP-VP1802-S combines the 7.35M-cell Versal Premium VP1802 with 140 GTM and 28 GTYP transceivers, three FMC+, six QSFP-DD and six NovaRay expansion positions. Dense board-level fan-out for multi-interface RTL partitioning, 400G-class networking bring-up, high-throughput datapaths and pre-silicon hardware\/software integration.\u003c\/p\u003e\n\u003cp\u003eTwo DDR4 SODIMM sockets, hardened PCIe Gen5 and Ethernet resources, programmable clocks and selectable FMC+ I\/O rails support repeatable subsystem integration without constraining the design to a single expansion format.\u003c\/p\u003e\n\u003ch4 id=\"fpga-specification\"\u003eFPGA Specification\u003c\/h4\u003e\n\u003ctable width=\"100%\"\u003e\u003ctbody\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eVersal Premium VP1802 Adaptive SoC\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSystem Logic Cells\u003c\/td\u003e\n\u003ctd\u003e7,351,960\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eCLB Flip-Flops\u003c\/td\u003e\n\u003ctd\u003e6,721,792\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLUTs\u003c\/td\u003e\n\u003ctd\u003e3,360,896\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eDistributed RAM\u003c\/td\u003e\n\u003ctd\u003e103 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eBlock RAM\u003c\/td\u003e\n\u003ctd\u003e4,941 blocks \/ 174 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eUltraRAM\u003c\/td\u003e\n\u003ctd\u003e2,549 blocks \/ 717 Mb\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDSP Engines\u003c\/td\u003e\n\u003ctd\u003e14,352\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eProcessing and Memory\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eApplication Processing Unit\u003c\/td\u003e\n\u003ctd\u003eDual-core Arm Cortex-A72\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eReal-Time Processing Unit\u003c\/td\u003e\n\u003ctd\u003eDual-core Arm Cortex-R5F\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eNoC-to-PL Ports\u003c\/td\u003e\n\u003ctd\u003e100 master \/ 100 slave\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eDDR Memory Controllers \/ Bus Width\u003c\/td\u003e\n\u003ctd\u003e4 \/ 256-bit\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eTransceivers and Hardened IP\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGTYP Transceivers\u003c\/td\u003e\n\u003ctd\u003e28 at up to 32.75 Gb\/s\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eGTM Transceivers\u003c\/td\u003e\n\u003ctd\u003e140 at up to 58 Gb\/s; 70 paired channels at up to 112 Gb\/s\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCIe with DMA (CPM5)\u003c\/td\u003e\n\u003ctd\u003e2 × Gen5 ×8\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003ePL PCIe Gen5\u003c\/td\u003e\n\u003ctd\u003e2 × Gen5 ×4\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e100G Multirate \/ 600G Ethernet MAC\u003c\/td\u003e\n\u003ctd\u003e8 \/ 7\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003e600G Interlaken \/ Crypto Engines\u003c\/td\u003e\n\u003ctd\u003e3 \/ 4\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003ePackage\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDevice\u003c\/td\u003e\n\u003ctd\u003eXCVP1802-2MSELSVC4072\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003ePackage \/ Footprint \/ Pitch\u003c\/td\u003e\n\u003ctd\u003eLSVC4072 \/ 65 × 65 mm \/ 1.0 mm\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eXPIO \/ MIO\u003c\/td\u003e\n\u003ctd\u003e132 DDR-only, 516 DDR+PL, 54 PL-only \/ 78 MIO\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\u003c\/table\u003e\n\u003ch4 id=\"features\"\u003eFeatures\u003c\/h4\u003e\n\u003ctable width=\"100%\"\u003e\u003ctbody\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eFPGA and Memory\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eAdaptive SoC\u003c\/td\u003e\n\u003ctd\u003eVersal Premium XCVP1802-2MSELSVC4072\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eDDR4 SODIMM\u003c\/td\u003e\n\u003ctd\u003e2 sockets, up to 2,666 MT\/s\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eHigh-Speed Expansion\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFMC+ 0 \/ 1\u003c\/td\u003e\n\u003ctd\u003e24 GTM lanes + 34 LVDS I\/Os each; 1.0 \/ 1.2 \/ 1.5 V selectable\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eFMC+ 2\u003c\/td\u003e\n\u003ctd\u003e20 GTYP lanes + 34 LVDS I\/Os; 1.0 \/ 1.2 \/ 1.5 V selectable\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSFP-DD\u003c\/td\u003e\n\u003ctd\u003e6 positions, 8 GTM lanes each; 400G optical-module support\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eNovaRay \/ NVAF\u003c\/td\u003e\n\u003ctd\u003e6 positions: 5 × 8 GTM lanes; 1 × 8 GTYP lanes\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003ePeripheral and Control\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eJTAG \/ UART\u003c\/td\u003e\n\u003ctd\u003e14-pin JTAG \/ 2 × USB-C UART\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eStorage\u003c\/td\u003e\n\u003ctd\u003emicroSD; 2 × 128 MB QSPI flash\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eConnectivity\u003c\/td\u003e\n\u003ctd\u003eUSB 2.0; Gigabit Ethernet; 2 × I2C\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003eUser I\/O\u003c\/td\u003e\n\u003ctd\u003e16-position DIP switch; 3 push buttons; 12 LEDs\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:Ivory;\"\u003e\u003ctd colspan=\"2\"\u003e\u003cstrong\u003eClock, Power and Mechanical\u003c\/strong\u003e\u003c\/td\u003e\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eClock Generator\u003c\/td\u003e\n\u003ctd\u003eSi5391; DDR 200 MHz; FMC+ 125 MHz; QSFP-DD \/ NVAF 156.25 MHz\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003ePower\u003c\/td\u003e\n\u003ctd\u003eATX input\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCooling\u003c\/td\u003e\n\u003ctd\u003eDynatron J5 active air cooler\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr style=\"background-color:WhiteSmoke;\"\u003e\n\u003ctd\u003ePCB\u003c\/td\u003e\n\u003ctd\u003e305 × 210 × 3.35 mm (estimated); 28 layers\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\u003c\/table\u003e\n\u003ch4 id=\"whats-included\"\u003eWhat's Included\u003c\/h4\u003e\n\u003cul\u003e\n\u003cli\u003eMFP-VP1802-S main board\u003c\/li\u003e\n\u003cli\u003e16 GB DDR4 SODIMM × 1\u003c\/li\u003e\n\u003cli\u003e32 GB microSD card\u003c\/li\u003e\n\u003cli\u003e12 V \/ 12 A power adapter\u003c\/li\u003e\n\u003cli\u003eDynatron J5 active cooler\u003c\/li\u003e\n\u003cli\u003eDocumentation and reference-design media supplied by CodeRobin\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch4 id=\"resources-downloads\"\u003eResources \u0026amp; Downloads\u003c\/h4\u003e\n\u003cul\u003e\n\u003cli\u003e\u003ca href=\"https:\/\/huins.com\/en\/product\/view.php?part1_idx=1\u0026amp;part_idx=45\u0026amp;idx=109\" target=\"_blank\" rel=\"noopener\"\u003eHUINS MFP-VP1802-S official product page\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/versal-premium-product-selection-guide\" target=\"_blank\" rel=\"noopener\"\u003eAMD Versal Premium Series Product Selection Guide\u003c\/a\u003e\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003cp\u003eFull documentation including user manual, pinout list and schematics is provided by CodeRobin.\u003c\/p\u003e\n","brand":"HUINS","offers":[{"title":"Default Title","offer_id":55688459190648,"sku":"MFP-VP1802-S","price":24266.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0051\/1564\/1942\/files\/01-mfp-vp1802-s-main-front.jpg?v=1791004074","url":"https:\/\/coderobin.com\/products\/huins-mfp-vp1802-s-versal-premium-vp1802-adaptive-soc-asic-rapid-prototyping-platform","provider":"CodeRobin FPGA","version":"1.0","type":"link"}