{"product_id":"alinx-axvu13p-xilinx-virtex-ultrascale-xcvu13p-fpga-development-board","title":"ALINX AXVU13P: Xilinx Virtex UltraScale+ XCVU13P FPGA Development Board","description":"\u003cul\u003e\n\u003cli\u003e\u003ca href=\"#Features\"\u003eFeatures\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#Whats_Included\"\u003eWhat's Included\u003c\/a\u003e\u003c\/li\u003e\n\u003cli\u003e\u003ca href=\"#Quick_Links\"\u003eResources \u0026amp; Downloads\u003c\/a\u003e\u003c\/li\u003e\n\u003c\/ul\u003e\n\u003ch4\u003eDescription\u003c\/h4\u003e\n\u003cp\u003eAXVU13P is a flagship High Performance PCIE3.0 x16 Card with XCVU13P FPGA, 3x HPC FMC+, 1x SODIMM, enabling high signal processing bandwidth, rich expandability. Ideal for data center AI\/HPC acceleration, 100G+ Network, high-end ASIC\/SoC prototyping and verification, radar\/communication real-time signal processing and other ultra-large-scale, low-latency, high-bandwidth advanced computing and communication applications.\u003c\/p\u003e\n\u003ch5\u003eFPGA Specification\u003c\/h5\u003e\n\u003cstyle\u003e\n    table#table_comparison tr:nth-child(even) { background-color:WhiteSmoke; }\n\u003c\/style\u003e\n\u003ctable id=\"table_comparison\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eFPGA\u003c\/td\u003e\n\u003ctd\u003eXCVU13P-2FHGB2104I\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSpeed Grade\u003c\/td\u003e\n\u003ctd\u003e-2\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eChip Level\u003c\/td\u003e\n\u003ctd\u003eIndustrial Grade\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eWorking Temperature\u003c\/td\u003e\n\u003ctd\u003e-40℃~85℃\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSystem Logic Cells (K)\u003c\/td\u003e\n\u003ctd\u003e3,780\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCLB Flip-Flops (K)\u003c\/td\u003e\n\u003ctd\u003e3,456\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCLB LUTs (K)\u003c\/td\u003e\n\u003ctd\u003e1,728\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMax. Distributed RAM (Mb)\u003c\/td\u003e\n\u003ctd\u003e48.3\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eTotal Block RAM (Mb)\u003c\/td\u003e\n\u003ctd\u003e94.5\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUltraRAM (Mb)\u003c\/td\u003e\n\u003ctd\u003e360.0\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDSP Slices\u003c\/td\u003e\n\u003ctd\u003e12,288\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePeak INT8 DSP (TOP\/s)\u003c\/td\u003e\n\u003ctd\u003e38.3\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCIe® Gen3 x16\u003c\/td\u003e\n\u003ctd\u003e4\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e150G Interlaken\u003c\/td\u003e\n\u003ctd\u003e8\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e100G Ethernet w\/ KR4 RS-FEC\u003c\/td\u003e\n\u003ctd\u003e12\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eGTY 28.21 Gb\/s Transceivers\u003c\/td\u003e\n\u003ctd\u003e76\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMax. Single-Ended HP I\/Os\u003c\/td\u003e\n\u003ctd\u003e702\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch4 id=\"Features\"\u003eBoard Features\u003c\/h4\u003e\n\u003cstyle\u003e\n  table#table_features tr:nth-child(even) { background-color:WhiteSmoke; }\n\u003c\/style\u003e\n\u003ctable id=\"table_features\"\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eDDR4\u003c\/td\u003e\n\u003ctd\u003e1x SODIMM socket supports up to 16GB.\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eQSPI Flash\u003c\/td\u003e\n\u003ctd\u003e2x 128MB, for FPGA bin file and user data storage\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eCrystal Oscillator\u003c\/td\u003e\n\u003ctd\u003e2x 200MHz Differential Crystal, Reference Clock for the FPGA and DDR4\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eFMC+\u003c\/td\u003e\n\u003ctd\u003e3x \u003cb\u003eFMC+\u003c\/b\u003e, compatible with FMC+ and FMC\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCI Express 3.0\u003c\/td\u003e\n\u003ctd\u003ex16 lane, up to 8G Baud each lane\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eSMA\u003c\/td\u003e\n\u003ctd\u003e2x SMA Differential I\/O, connected to FPGA HPIO, for customer differential signal I\/O testing.\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eDIP Switch\u003c\/td\u003e\n\u003ctd\u003e1x 4-bit, for simple testing.\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eUSB UART\u003c\/td\u003e\n\u003ctd\u003efor Serial Communication with PC\/Devices\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eJTAG\u003c\/td\u003e\n\u003ctd\u003e14-pin 2.00mm Standard JTAG port for Program Debug and Download\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eExpansion Port\u003c\/td\u003e\n\u003ctd\u003e1x 14-pin 2.54mm port, connected to FPGA HPIO (10 pin)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eLED\u003c\/td\u003e\n\u003ctd\u003e8x LEDs: 1 Power, 1 DONE, 4 User, 2 UART (TX\/RX); 2 User (on PCI Bracket)\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePush-Buttons\u003c\/td\u003e\n\u003ctd\u003e1x: Reset\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch5\u003ePower Supply \u003c\/h5\u003e\n\u003cp\u003eVoltage Input: +12 V DC, PCIE slot or PCIE 8-pin\u003c\/p\u003e\n\u003cp\u003eCurrent Input: Max. Current 15 A\u003c\/p\u003e\n\u003ch5 id=\"Whats_Included\"\u003eWhat's Included\u003cbr\u003e\n\u003c\/h5\u003e\n\u003ctable\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eFPGA Board\u003c\/td\u003e\n\u003ctd\u003e1\u003c\/td\u003e\n\u003ctd\u003eDC Fan (installed)\u003c\/td\u003e\n\u003ctd\u003e1\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003eMini USB Cable\u003c\/td\u003e\n\u003ctd\u003e1\u003c\/td\u003e\n\u003ctd\u003eProgramming Cable\u003c\/td\u003e\n\u003ctd\u003e1 set\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003e12V Power Adapter\u003c\/td\u003e\n\u003ctd\u003e1\u003c\/td\u003e\n\u003ctd\u003ePCI Bracket\u003c\/td\u003e\n\u003ctd\u003e1\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch5\u003eDimensions\u003c\/h5\u003e\n\u003ctable\u003e\n\u003ctbody\u003e\n\u003ctr\u003e\n\u003ctd\u003eDimension\u003c\/td\u003e\n\u003ctd\u003e251.00mm x 111.15mm\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003ctr\u003e\n\u003ctd\u003ePCB\u003c\/td\u003e\n\u003ctd\u003e18 Layer, Independent GND and Power Layers\u003c\/td\u003e\n\u003c\/tr\u003e\n\u003c\/tbody\u003e\n\u003c\/table\u003e\n\u003ch4 id=\"Quick_Links\"\u003eResources \u0026amp; Downloads\u003c\/h4\u003e\n\u003cp\u003e\u003ca title=\"ALINX AXVU13P: Xilinx Virtex UltraScale+ XCVU13P FPGA Development Board\" href=\"https:\/\/raw.githubusercontent.com\/fpgauk\/pdf\/main\/alinx\/axvu13p\/AXVU13P_User_ManualV1.0.pdf\" target=\"_blank\"\u003eAXVU13P User Manual (PDF)\u003c\/a\u003e\u003c\/p\u003e\n\u003cp\u003e\u003ci\u003eFull documentation including Schematics, Demo projects (if applicable) will be provided by CodeRobin.\u003c\/i\u003e\u003c\/p\u003e\n","brand":"ALINX","offers":[{"title":"Default Title","offer_id":55515987673464,"sku":"AXVU13P","price":13658.99,"currency_code":"GBP","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0051\/1564\/1942\/files\/AXVU13P_Off_01.jpg?v=1774793931","url":"https:\/\/coderobin.com\/products\/alinx-axvu13p-xilinx-virtex-ultrascale-xcvu13p-fpga-development-board","provider":"CodeRobin FPGA","version":"1.0","type":"link"}